Hardware Security
Ring Oscillator PUF on FPGA
Implemented a Ring Oscillator based Physically Unclonable Function on Tang Nano 20K FPGA to generate unique device keys without storing secrets in non-volatile memory.
Critical Infrastructure Modernization, Embedded Firmware (C/C++), Network Engineering (TCP/IP, DLR), and Hardware Security (FPGA).
I bridge the gap between legacy hardware and modern automation, deploying fault-tolerant systems in the field.
TCP/IP, DNS, DHCP, Routing/Switching, EtherNet/IP, DLR, Fiber Optic Troubleshooting
C, C++, Python, Verilog, VHDL, FreeRTOS, ESP32, FPGA (Tang Nano/Xilinx)
Studio 5000 (Allen-Bradley), Stratix Switches, SCADA, PLC Ladder Logic, Modbus
Megger ADX6 (Motor Testing), Oscilloscope, Logic Analyzer, PCB Design (Altium)
MQTT, CoAP, SPI, I2C, UART, PROFINET, ControlNet
Hardware Security
Implemented a Ring Oscillator based Physically Unclonable Function on Tang Nano 20K FPGA to generate unique device keys without storing secrets in non-volatile memory.
Embedded Systems
Built a terrain-capable robot using an LPC2148 microcontroller to detect metallic landmines and report GPS coordinates via GSM.
Automotive Integration
Designed the Brake System Plausibility Device and wiring harness for an electric Formula SAE racecar, aligned with Formula Bharat safety requirements.
Led the electronics subsystem for an electric racecar including BSPD design, ECU integration, wiring harness development, and track-side debugging.
Northeastern University · Boston, MA
2024 - 2026 (expected)
MES Pillai College of Engineering · Mumbai
2019 - 2023